In modern electronic circuits, such as, for example, input/output (IO) buffers, it is desirable to control the variation in output impedance of the IO buffers for a variety of reasons, including, but not limited to, transmission line matching, minimizing switching noise (e.g., di/dt), optimizing signal swing, etc. In many high-speed, high-bandwidth applications, such as, for example, memory interfacing (e.g., double data rate 3 (DDR3) or DDR4 memory), it is important to control the output impedance of the buffer within a specified tolerance limit over a prescribed range of operating conditions so as to reduce signal degradation. It is also important to control pull-up and pull-down impedances of the buffer in such a way that the relative difference between the impedances is minimized.
In order to achieve such tight control of output impedance, a buffer, often referred to as a compensated buffer, is typically employed which is adapted to compensate for variations in integrated circuit (IC) process, supply voltage and/or temperature (PVT) conditions to which the buffer may be subjected. In one implementation, a PVT compensated buffer utilizes a compensation circuit including a PVT control block which monitors a deviation in output impedance of a block of one or more reference devices matched to corresponding devices (e.g., pre-drivers) in an output stage of the buffer to be compensated. The PVT control block generates a set of digital bits, often referred to as “PVT bits” (PVTBITS), that are used to control the reference devices (e.g., turning the devices on or off) so as to maintain a constant output impedance. The output impedance of the reference block will be a function of the number of devices in the block that are turned on or off at any given time. These PVT bits are also fed to the buffer to control the output impedance of the buffer output stage devices in a similar manner. The number of pre-drivers in the buffer output stage is directly proportional to the number of digital control bits.
In the context of metal-oxide-semiconductor (MOS) transistor devices, since p-channel MOS (PMOS) transistor devices and n-channel MOS (NMOS) transistor devices do not generally track one another, pull-up devices (which typically employ PMOS transistors) are traditionally compensated separately from pull-down devices (which typically employ NMOS transistors), thereby resulting in significantly increased complexity of the design, reduced IC layout area efficiency, and higher relative error between pull-up and pull-down impedances. Accordingly, such conventional approaches to buffer compensation are impractical and/or undesirable.